In many 3D integrated circuits, transistor-based memory cells utilize fuses, thus making the memory cells “one-time programmable”. One issue with the use of such fused memory cells is that the programming creates permanent changes to the silicon, which can be easily detected and reversed engineered with physical inspection.
Another issue with 3D integrated circuits is the lack of control of peripheral chips from a main controller chip. Often times, these peripheral chips are always powered up and running, even when not necessary.
As such, it is desirable to provide an interposer for an integrated circuit that allows for multiple-time programming. It is also desirable to provide an integrated circuit with the ability for control of peripheral functional chips. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.